This invention relates in general to the handling of mail within a mail sorting machine which is operable to receive a stack of envelopes, separate the envelopes from each other and successfully convey each of these envelopes to its designated sort bin through a single guideway formed by a plurality of deflecting gates. In particular, this invention deals with a microprocessor controlled method and system for automatically sorting the envelopes into common groups, assigning each group a particular sort bin and for generating a coded bin designation signal representative of the selected sort bin.
The volume of mail handled daily by large businesses, institutions and governmental entities has reached the point where new techniques and machines for automatically handling and sorting this mail more efficiently and economically must be developed. Although several machines for handling and sorting mail are presently available, these prior machines have not proven to be satisfactory for several reasons. For example, the presently existing mail sorting machines are normally very complex in design and operation and require the services of an operator to read a sort code imprinted on each envelope. These machines are typically comprised of an array of metal bands which form a plurality of guideways for transferring the received envelopes from a central sorting location to one of the machine's sort bins. In these machines, incoming envelopes are initially separated and successively provided to a read station where an operator reads sorting information imprinted on each envelope. The operator must then determine where this envelope is to be deposited and make the appropriate entry on the machine's keyboard to introduce the envelope into the guideway corresponding to the designated sort bin. This type of sorting technique is extremely inefficient because each envelope must be stopped at the read station so that the operator can read the sorting information imprinted on the envelope. Additional time is wasted waiting for the operator to determine where the envelope should be deposited and then depressing the button corresponding to the designated sort bin. Finally, envelopes sorted in this way are often directed to the wrong sort bin due to an error on the part of the operator.
It is therefore an object of the present invention to provide a microprocessor controlled system and technique for quickly and reliably reading the sort code imprinted on each envelope, sorting the envelopes into common groups, assigning each group a sort bin and generating a coded bin designation signal representative of the selected bin.
The microprocessor controlled system of the present invention receives sorting information from a reader which is positioned adjacent to the guideway through which the separated envelopes are being transported. This reader is capable of reading sorting information imprinted on each envelope as the envelope moves past the reader. As a result, the envelope does not have to be stopped for viewing by the reader or an operator thereby significantly increasing the speed at which envelopes may be sorted.
During the first pass, all of the envelopes to be sorted are run though the machine. The microprocessor causes each of these envelopes to be deposited in a designated sort bin in accordance with a sort table which was programmed into the microprocessor prior to the first pass. The microprocessor also compiles information concerning the zip code associated with each envelope moving through the machine during the first pass. In particular, the microprocessor creates a list of each zip code and maintains a count of the number of envelopes having a particular zip code.
Once the first pass is completed, the microprocessor assembles the compiled zip codes into common groups. In particular, all envelopes with the same five digit zip code are placed in a common group if there are ten or more envelopes with this zip code. Envelopes are also assembled into a common group if there are fifty or more envelopes with the same first three digits exclusive of the envelopes which have already been placed in a common group because there are ten or more of them with the same five digit zip code. The remaining envelopes are then put into a residual group. The microprocessor then assigns each of these common groups a bin location and assembles these bin locations into a sort table which is used during the second pass to direct each of the envelopes into its appropriate sort bin. The computing system also provides a list of instructions for loading of the envelopes during the second pass and for identifying which group of envelopes are stored in which sort bin.
The envelopes are then gathered for a second pass and put into the mail sorting machine in accordance with the instructions. During the second pass, the reader once again reads the sort code imprinted on each envelope as the envelope moves past the reader.
The microprocessor then compares the envelope's sort code with the sort table created by the computing system after the first pass and generates a coded bin designation signal which is representative of the sort bin in which the envelope is to be deposited. The coded bin designation signal moves through the mail sorting machine in synchronization with its associated envelopes to cause this envelope to be directed to its designated sort bin.
An additional object of the present invention is to provide a microprocessor implemented system of the character described wherein the amount of memory needed to implement the system is significantly reduced to thereby provide a substantial cost savings. Since the sort codes are stored within the microprocessor on a temporary basis, these codes are stored within random-access-memory units. The cost of random-access-memory is rather signficant when compared with the other components of the microprocessor. As a result, a substantial cost savings can be obtained by limiting the required amount of random-access-memory.
It is a further object of the present invention to provide a microprocessor implemented system of the character described wherein the amount of memory to implement the system is significantly reduced to thereby substantially increase the speed of operation. By reducing the number of memory locations, the speed of the central processing unit is correspondingly increased.
Other and further objects of this invention, together with the features of novelty appurtenant thereto, will appear in the course of the following description.